Overview

Ends a layout and returns to the original clock divider

Discussion

The BufferDownV2 module is used to implement multi-layouting and is used in conjunction with the BufferUpV2 module. The BufferDownV2 module terminates a layout and returns processing to a layout with a lower clock divider (higher priority, smaller block size).

The module supports multiple input and output pins and all downstream modules will be in the new layout. The input wires must all be in the same clock divider, but they can all have different sizes, sample rates, and data types. All output wires are returned to the same base layout.

The module allows you to decrease the clock divider by an integer factor bufferDownFactor (BUFFER_DOWN_FACTOR). This causes the output block size to decrease by bufferDownFactor as well. Smaller clock dividers end up going into higher priority layouts.

The module also allows you to specify the output layoutSubID (LAYOUT_SUB_ID). The layoutSubID allows you to run multiple layouts at the same clockDivider but in different layouts. For example, you might have multiple layouts all at a clock divider of 1 operating in a SMP core system. Whereas V1 of this module will force all processing for a particular clockdivider value into the base layout for that clockdividier, V2 allows separate layouts within the same clockdivider for more advanced multicore implementations.

This module introduces a sample latency of the input pin's block size.

Type Definition

-Not Shown-

Pins

Input Pins

Name: in1

Description: audio input

Data type: {float, int, fract32}

Channel range: Unrestricted

Block size range: Unrestricted

Sample rate range: Unrestricted

Complex support: Real and Complex

Output Pins

Name: out1

Description: audio output

Data type: {float, int, fract32}

MATLAB Usage

File Name: buffer_down_v2_subsystem.m