Overview

FIR filter with multi channel coefficients

Discussion

The FIR Module implements a direct convolution N-order Finite Impulse Response filter. The module operates on multiple channels with separate coefficients per channel. The filter coefficients are stored in the array, coeffs, in normal order. The size of the array is coeffsInc x numChannels. Coefficients length per channel, coeffsInc, is numTaps + 1 + ~rem(L, 2) and value at last location must be 0. This is needed for SIMD operations on SHARC processors To make coefficients pointer is even aligned per channel, coeffsInc is always even number. i.e. if the tap length argument L is even then coeffsInc = L + 2, otherwise coeffsInc = L + 1. If the L is even, user has to make sure that the last two locations per channel are zeros. The state variable array is of size (numTaps + blockSize + 3) x numChannels.

The module is optimized in assembly on the SHARC and the Blackfin. The SHARC implementation utilizes SIMD if the length of the filter is even and this reduces the processing load significantly. If you have an odd order filter, you can zero pad the filter with one additional zero coefficient and realize the benefits of SIMD.

On the ADI SHARC+ platforms, except ADSP-2157x and ADSP-2158x, the module make use of FIR Accelerators, in legacy mode, to optimize the processing time. On SHARC+ processor, additional memory is allocated for accelerator TCB with size of numAcceleratorChannels*13. The processing load is distributed as 2 channels processing in FIRA is equivalent to 1 channel core processing. i.e. the FIRA channels=numChannels-floor(numChannels/3). As the accelerators access data by DMA, when the dm and pm caches are enabled, extra cycles are needed to maintain cache coherence. It is highly recommended to increase the allocation priority of this module instance in the signal flow to have a larger chance to allocate in the AWE fast heaps. In this way, the overhead from accelerator can be minimized. If any of this module instances allocated in the AWE slow heap, please note that the CPU load might be higher than without FIRA due to cache coherence maintenance. Maximum number of channels that can be processed in FIR Accelerator is limited to 32 and the remaining channels are processed by the core. i.e. FIRA channels=min(numChannels-floor(numChannels/3), 32)

On the processors of 2159x where 2 FIR accelerators are available with dual SHARC+ cores, two FIR accelerators are used which further reduces the processing load of multiple channels with 4 channels can be processed in parallel with 1 channel processing in the core. i.e. the FIRA channels=numChannels-floor(numChannels/5). Please note that this module is not multi-core safe i.e. same module can not be used in Sharc1 and Sharc2 at the same time.

Type Definition

typedef struct _ModuleFIRNChan
{
    ModuleInstanceDescriptor instance;            // Common Audio Weaver module instance structure
    INT32 numTaps;                                // Length of the filter.
    INT32 coeffsInc;                              // Length of the coefficient array per channel.
    INT32 stateIndex;                             // Index of the oldest state variable in the array of state variables.
    INT32 stateIndexAcc;                          // Index of the oldest state variable in the array of state variables, used for accelerators.
    FLOAT32* coeffs;                              // Filter coefficient array in normal order. The size of the array is (coeffsInc + 1) x numChannels. Each column contains the coefficients for a channel.
    FLOAT32* state;                               // State variable array. The size of the array equals stateLen * numChannels.
    void * hardware_specific_struct_pointer;      // This is the internal TCB array used for ADI FIR accelerator
} ModuleFIRNChanClass;

Variables

Properties

Name	Type	Usage	isHidden	Default value	Range	Units
numTaps	int	const	0	31	1:1:5000	samples
coeffsInc	int	const	1	32	Unrestricted
stateIndex	int	state	1	0	Unrestricted
stateIndexAcc	int	state	1	0	Unrestricted
coeffs	float*	parameter	0	[32 x 1]	Unrestricted
state	float*	state	1	[66 x 1]	Unrestricted
hardware_specific_struct_pointer	void *	state	1		Unrestricted

Pins

Input Pins

Name: in

Description: audio input

Data type: float

Channel range: Unrestricted

Block size range: Unrestricted

Sample rate range: Unrestricted

Complex support: Real

Output Pins

Name: out

Description: audio output