(8.D.2.7) Delaying Control Signals

You may encounter a situation where you want to delay the action of a control signal by a fixed or variable amount of time. As control signals typically are processed at a slower rate than audio in your design, running the control signal through a delay block running at the native sampling rate will use an unnecessarily large amount of RAM unless you configure the delay to operate at the same lower sample rate and block size as the control signal itself.

Example 1: Using a control signal coming in on the input pin

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In this example, the control signal which we wish to delay at a lower sample rate is coming in on the layout’s input pin on channel 2 at 48 kHz with a block size of 32. Channel 1 carries the audio data which will have its gain adjusted by the delayed control signal.

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The first sample rate reduction occurs as a result of the Block Statistics module which outputs a block size of 1 regardless of the input Block Size. The output sample rate is the input sample rate divided by the input block size. 48000/32 = 1500 Hz.

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In order to reduce the sample rate further, we have to buffer up after which we can use a decimator. The buffer up factor and the decimation factor are set to the same value (32) resulting in a signal of block size 1 which is at 1500/32 = 46.875 Hz. This sets the resolution of the delay setting to 1/46.875 = 21.3 msec per sample.

The delay module is now operating with a block size of 1 at 46.875 Hz. In this example, 200 samples will result in a delay of about 4.27 seconds. If we had run the delay line at 48000 Hz, this same delay would have required 204,800 samples.

Following the Delay module, we use a FIR Interpolation module to return the signal sampling rate to 1500 Hz (48000/32). Finally, a BufferDown module reduces the block size to 1 which makes it equivalent to a control signal coming from a DC Source.

The total delay time includes the latency of the Buffering, Decimation, and Interpolation stages in addition to the Delay module itself.

View the accumulated delay by selecting View->Accumulated Delay.

The accumulated delay in this example is 6591 samples @ 1500 Hz or 4.394 seconds. The Delay itself contributes 4.267 seconds, so the delay contribution of the additional processing is about 0.127 seconds.

Example 2: Using a control signal coming from a DC Source.

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This is very much like the first example, with the exception that we set the DC Source to run at 1500 Hz (input sample rate/input block size) with a Block Size of 1, so the first BlockStatistics module is not needed.

Options and considerations:

You can use IIR based decimators and interpolators instead of FIR based ones. These will have different resource requirements (RAM, CPU load) and latency.

When using the FIR interpolator, if the filter length is too short, you will see artifacts in the delayed control signal.