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The first sample rate reduction occurs as a result of the Block Statistics module which outputs a block size of 1 regardless of the input Block Size. The output sample rate is the input sample rate divided by the input block size. 48000/32 = 1500 Hz.
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In order to reduce the sample rate further, we have to buffer up after which we can use a decimator. The buffer up factor and the decimation factor are set to the same value (32) resulting in a signal of block size 1 which is at 1500/32 = 46.875 Hz. This sets the resolution of the delay setting to 1/46.875 = 21.3 msec per sample.
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The delay module is now operating with a block size of 1 at 46.875 Hz. In this example, 200 samples will result in a delay of about 4.27 seconds. If we had run the delay line at 48000 Hz, this same delay would have required 204,800 samples.
Following the Delay module, we use a FIRInterpolation FIR Interpolation module to return the signal sampling rate to 1500 Hz (48000/32). Finally, a BufferDown module reduces the block size to 1 which makes it equivalent to a control signal coming from a DC Source.
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The total delay time includes the latency of the Buffering, Decimation, and Interpolation stages in addition to the Delay module itself.
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The accumulated delay in this example is 6591 samples @ 1500 Hz or 4.394 seconds. The Delay itself contributes 4.267 seconds, so the delay contribution of the additional processing is about 0.127 seconds.
Example 2: Using a control signal coming from a DC Source.
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You can use IIR based decimators and interpolators instead of FIR based ones. These will have different resource requirements (RAM, CPU load) and latency.
When using the FIR interpolator, if the filter length is too short, you will see artifacts in the delayed control signal.
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