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The ClockDivider field in Properties when left blank will default to 1A0. This represents clock divider “1”, subLayoutID “A” and instance “0”. The instance value can be changed to move that module to a designated core (4 virtual cores by default in Designer [0,3]) and profiled separately. The clock divider changes as a result of buffering up or down.

Note: The clock divider field is only user editable for source modules and automatically assigned for the rest.

For example, if 1A0 were changed to 1A1, profiling for that module would could be seen on the second instance on the Server:

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NOTE: By default, 4 virtual instances are created in Designer Native. These can be changed in Server Preferences, and memory will be divided between them:

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Buffer Up and Buffer Down

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• The Buffer Up module supports multiple input and output pins

  • The input wires must all be in the same clock divider

• This module introduces a sample latency of buffUpFactor times the input pin’s block size

• Large clock dividers go into lower priority layouts

• User can designate layouts ‘A’ through ‘P’ (16 total)

• Supports buffering up by whole-number multiples

More information on BufferUpV2 available here: (8.D.2.6) BufferUpV2

Buffer Down

Ends a layout and returns to the original clock divider (higher priority, smaller block size)

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