Release 4.1 is adding
Can be on different Hexagon DSPs
Can be on different clockDividers
Can utilize different block sizes and sample rates
TDM initialization follows a prescribed sequence including initializing bitclk first followed by the frame sync.
Synchronous TDM ports time align themselves automatically to within 1 sample.
Asynchronous serial ports including an ASRC and output data at a fixed sample rate and block size.
Synchronization Modes
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Notice: Pre-Release Documentation |
Release 4.1 is adding
Can be on different Hexagon DSPs
Can be on different clockDividers
Can utilize different block sizes and sample rates
TDM initialization follows a prescribed sequence including initializing bitclk first followed by the frame sync.
Synchronous TDM ports time align themselves automatically to within 1 sample.
Asynchronous serial ports including an ASRC and output data at a fixed sample rate and block size.
Synchronization Modes
The serial port modules support synchronous and asynchronous operation. In synchronous operation, the serial ports are all clocked off the same master clock. In asynchronous operation, the serial port has a different clock that is not equal to the master clock. Operation can be further classified as
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All other properties are taken directly from the AudioLite APIs and are used when opening the port.
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Timing Information Output Pin
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Error Code | Meaning |
-1000 | Config or start-time. Failed to open the TDM port with the given configuration settings. |
-1001 | Config or start-time. Failed to set the DMA callback (should never happen). |
-1002 | Config or start-time. Failed to get the system wide time stamp resolution (should never happen) |
-1003 | Config or start-time. Failed to get configuration of the Synchronous Master serial port. This can occur if a Synchronous Master port was not defined. |
-1004 | Config or start-time. Failed to start real-time audio on the port. |
-1005 | Config or start-time. Failed to get details of the port’s DMA buffer (should never happen). |
-1006 | Real-time. Unable to fetch the port’s ping-pong buffer details including time stamp and ISR counter (should never happen). |
-2001 | Real-time. Unable to fetch the Synchronous Master port’s ping-pong buffer details including time stamp and ISR counter (should never happen). |
-2003 | Real-time. Error reading data from the ASRC algorithm (should never happen). |
-2005 | Real-time. Failure writing data into the output FIFO (should never happen). |
Run-time Reconfiguration of Asynchronous TDM Ports
The asynchronous ports allow the device properties to be changed at run-time. Use the following sequence of operations to reconfigure the port:
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The Primary Audio Core (PAC) initializes and loads its AWB first.
All TDM ports on the PAC are initialized using the sequence above.
Audio start command starts DMA on the PAC. Audio is active.
PAC signals GPDSP0 to start initializing
GPDSP0 loads its own AWB
GPDSP0 initializes the TDM modules in its AWB
TDM audio interrupts start on GPDSP0
GPDSP0 signals the PAC that it is done initializing
The PAC signals GPDSP0 to pump audio
PAC signals GPDSP1 to start initializing
GPDSP1 loads its own AWB
GPDSP1 initializes the TDM modules in its AWB
Audio interrupts start on GPDSP1
GPDSP1 signals the PAC that it is done initializing
The PAC signals GPDSP1 to pump audio
Early audio is fully initialized
TDM Port Latency
The input to output latency on the SA8255 ADP was measured using a loopback test. The signal path was:
TDM Output → A2B → DAC → ADC → A2B → TDM Input
The measurement included the digital buffering latency of Audio Weaver and also the latency through the analog codec. With a 0.25 msec block size (12 samples at 48 kHz), we measured a total delay of 1.6 msec. This corresponded to a 0.5 msec Audio Weaver processing delay, and a 1.1 msec analog delay. More details can be found here.
Usage Guidelines
Do not make the block sizes of your TDM ports too large. There is a limited amount of DMA memory on the Snapdragon and you may exceed this. (Audio Weaver testing has been with block sizes up to 5.0 msec.)
You are only allowed to define a single TDM port as being the Synchronous Master. If you define multiple ports as Synchronous Master, then you will get a build error.
You are allowed to place the TDM Port modules into different threads. For example, one port operates at a block size of 1 msec and is placed in thread 1A. A second port operates at a block size of 5 msec and is placed in thread 5A. A third port operates at a block size of 1 msec and is placed in thread 1B.
Large block sizes lead to more efficient operation. You should restrict the small block sizes (0.25 and 0.5 msec) for use cases that require low latency. Other ports doing non-latency sensitive operations (like radio or Bluetooth), should use larger block sizes.
If you stop a port, it will stop the audio DMA and interrupts. The DMA memory is freed up. When you start the port, DMA memory is reallocated and DMA interrupts start again. SA ports will restart and be time aligned to the SM port. SU ports will restart and resynchronize themselves to the SM port.
The SM, SA, and SU ports have a single block size argument. This block size is used to set the block size of the DMA interrupt and also the block size at the output (or input) audio pins in Audio Weaver.
The AS port has separate sample rates and block sizes for the device configuration and the Audio Weaver configuration. After stopping an AS device, you can change the device block size and sample rate, and these new values will be used when the port is restarted. This feature is specifically for interfacing with Bluetooth devices.
TDM ports can only be accessed from the Hexagon DSPs. They are not available on the Arm.
On the SA8255, the DSPs are all part of the early audio boot sequence and thus all TDM ports must be initialized during early audio. On Nordy, only DSP0 is part of the early boot sequence. TDM ports can be on DSP0 and on DSP1 or DSP2 which are part of the late boot sequence.
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