...
The first sample rate reduction occurs as a result of the Block Statistics module which outputs a block size of 1 regardless of the input Block Size. The output sample rate is the input sample rate divided by the input block size. 48000/32 = 1500 Hz.
...
In order to reduce the sample rate further, we have to buffer up after which we can use a decimator. The buffer up factor and the decimation factor are set to the same value (32) resulting in a signal of block size 1 which is at 1500/32 = 46.875 Hz.
...
The delay module is now operating with a block size of 1 at 46.875 Hz. In this example, 200 samples will result in a delay of about 4.27 seconds. If we had run the delay line at 48000 Hz, this same delay would have required 204,800 samples.
Following the Delay module, we use a FIRInterpolation FIR Interpolation module to return the signal sampling rate to 1500 Hz (48000/32). Finally, a BufferDown module reduces the block size to 1 which makes it equivalent to a control signal coming from a DC Source.
...
The total delay time includes the latency of the Buffering, Decimation, and Interpolation stages in addition to the Delay module itself.
...