...

The Threading and Clock Dividers Application Note contains instructions for using multiple block sizes within a single system,  the modules necessary to do so, and the effects of doing so with respect to latency and priority handling.

...

Clock Divider

The ClockDivider field in Properties when left blank will default to 1A0. This represents clock divider “1”, subLayoutID “A” and instance “0”. The instance value can be changed to move that module to a designated core (4 virtual cores by default in Designer [0,3]) and profiled separately. The clock divider changes as a result of buffering up or down.

Note: The clock divider field is only user editable for source modules and automatically assigned for the rest.

Image Added

For example, if 1A0 were changed to 1A1, profiling for that module would could be seen on the second instance on the Server:

...

NOTE: By default, 4 virtual instances are created in Designer Native. These can be changed in Server Preferences, and memory will be divided between them:

...

Buffer Up and Buffer Down

...

The layoutSubID allows you to run multiple sets of modules at the same clockDivider in different layouts by setting the block size, and layoutSubID. For instance, the system input pin is always in layout 1A, and any layouts with the same clock divider could reside in 1B, 1C, alphabetically up to 1P. By changing to a higher block size, the user would be creating a second clock divider, where the user can add up to 16 layouts layout subIDs in this new block size (2A, 2B, 2C, etc.).

...

• When you build a layout like this, Audio weaver will split it into two layouts. The layouts are processed in separate threads because they have different block sizes. We support up to 16 threads (‘A’ through ‘P’)

• The higher priority layout will execute the far left and right sections of the system

• The lower priority layout will execute the middle section of the system

...

• The Buffer Up module supports multiple input and output pins

  • The input wires must all be in the same clock divider

• This module introduces a sample latency of buffUpFactor times the input pin’s block size

• Large clock dividers go into lower priority layouts

• User can designate layouts ‘A’ through ‘P’ (16 total)

• Supports buffering up by whole-number multiples

More information on BufferUpV2 available here: (8.D.2.6) BufferUpV2

Buffer Down

Ends a layout and returns to the original clock divider (higher priority, smaller block size)

...