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The Buffer Up module supports multiple input and output pins
The input wires must all be in the same clock divider
This module introduces a sample latency of buffUpFactor times the input pin’s block size
Large clock dividers go into lower priority layouts
User can designate layouts ‘A’ through ‘P’ (16 total)
Supports buffering up by whole-number multiples
More information on BufferUpV2 available here: (8.D.2.6) BufferUpV2
Buffer Down
Ends a layout and returns to the original clock divider (higher priority, smaller block size)
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